1. Field of the Invention
Embodiments of the invention relate to a method of manufacturing a semiconductor device. More particularly, embodiments of the invention relate to a method of manufacturing a flash memory device adapted to continuously input and output data regardless of relative time lapses.
This application claims priority under 35 USC § 119 to Korean Patent Application No. 2005-56191 filed on Jun. 28, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Conventional flash memory devices generally include a first gate structure adapted for use in a cell region, and a second gate structure adapted for use in a peripheral region. The first gate structure includes a tunnel oxide layer, a floating gate electrode, a dielectric layer pattern and a control gate electrode sequentially formed over a channel region selectively formed in the surface of a semiconductor substrate. The second gate structure has a structure analogous to conventional high voltage or low voltage transistors, and generally includes a gate insulation layer and a gate conductive layer sequentially formed over a channel region.
U.S. Pat. No. 6,023,085 discloses one example of a flash memory device incorporating these dual gate structures. FIGS. 1A to 1D are cross sectional views illustrating an exemplary method of manufacturing a conventional flash memory device having a dual gate structure.
Referring to FIG. 1A, a semiconductor substrate 10 having a cell region and a peripheral region is prepared. A shallow trench isolation (STI) process is carried out to form a trench isolation layer 12 in the semiconductor substrate 10. A first thin layer 16 adapted for use as part of the floating gate electrode is also formed. A tunnel oxide layer 14 is interposed between the first thin layer 16 and the semiconductor substrate 10. A dielectric layer 18 is then formed on the first thin layer 16 and the trench isolation layer 12.
A second thin layer 20 adapted for use as part of the control gate electrode is formed on the dielectric layer 18. The second thin layer 20 may be formed from a doped polysilicon layer having defined electrical characteristics (e.g., conductivity), as compared to those of an undoped polysilicon layer. A middle temperature oxide (MTO) layer 22 and a hard mask layer 24 formed from silicon nitride are sequentially formed on the second thin layer 20 to complete the control gate electrode.
Referring to FIG. 1B, the hard mask layer 24, the MTO layer 22, the second thin layer 20, the dielectric layer 18, the first thin layer 16, a portion of the trench isolation layer 12, and the tunnel oxide layer 14 are selectively removed from the peripheral region.
Referring to FIG. 1C, a third thin layer 25 adapted for use as a gate insulation layer is formed between the trench isolation layers 24 on the semiconductor substrate 10 in the peripheral region. An undoped polysilicon layer 26 is then formed on the hard mask layer 22 in the cell region, and on the third thin layer 24 and the trench isolation layer 12 in the peripheral region. Here, since a transistor formed in the peripheral region may be an NMOS transistor or a PMOS transistor, the undoped polysilicon layer 26 is used, in contrast to the doped second thin layer 20 adapted for use as part of the control gate electrode. Thus, an ion implantation process may be selectively performed on the undoped polysilicon layer 26 to form an NMOS transistor or a PMOS transistor in the peripheral region.
However, the undoped polysilicon layer 26 is generally formed with a very high step profile at the interface between the cell region and the peripheral region. This dramatic step different (e.g., very different material layer thicknesses over the two regions) may cause problems during subsequently performed fabrication processes.
Thus, as shown in FIG. 1D, the stepped portion of the undoped polysilicon layer 26 is removed by an etching process. After the hard mask layer 24 and the MTO layer 22 in the cell region are removed, the cell region and the peripheral region are patterned to form a first gate structure in the cell region and a second gate structure in the peripheral region. The first gate structure comprises a tunnel oxide layer, a floating gate electrode, a dielectric layer pattern and a control gate electrode. The second gate structure comprises a gate insulation layer and a gate conductive layer. A metal silicide layer is then formed on the control gate electrode of the first gate structure, the gate conductive layer of the second gate structure, and the semiconductor substrate.
There are several problems associated with the foregoing conventional method. For example, as shown in FIG. 2, foreign substances, such as particles lifted various fabrication processes may accumulate in the interface void formed by the removal of the stepped portion of the undoped polysilicon layer. Additionally, the removal of the stepped portion of the undoped polysilicon layer requires that an undoped polysilicon layer adapted for use as part of the control gate electrode be formed on the cell region and the peripheral region. Impurities must then be implanted only on the cell region using ion implantation process. However, since such impurities may not be sufficiently implanted into the polysilicon layer between the floating gate electrodes of the cell region, the desired conductive properties may not be obtained.